1.5.3
Computational Mesh
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The first pass at the Computational Mesh (Comesh pull-up) was my attempt to make the Occlusion Array into a viable hardware architecture. Robert Murphy took that naive model and converted it into an exciting pragmatic physical hardware design. Simulated in SPICE, Comesh exhibits:

–– very high logic density
–– a constant high-speed clock (300 MHz)
–– average power consumption
–– ease of manufacturability
–– backward compatibility with existing techniques
boundary math
architectures

distinction nets
occlusion array
∆ comesh

links
site structure

The Comesh architecture is based on and designed for boundary logic forms, and thus is particularly easy to layout and route. We expect it to deliver a reliable 300 MHz timing (for .18 micron technology), independent of the logic layout.

COMESH HARDWARE MODELS (overview)
COMPUTATIONAL MESH (examples)
COMPUTATIONAL MESH WITH PULL-UPS (examples)
DIAGONALIZATION OF THE CIRCUIT CONFIGURATION ARRAY

Place and Route

COMMON STRUCTURAL PATTERNS
LABELING THE CELL STRUCTURES
PLACE AND ROUTE LAYOUT DIAGRAMS*
PLACE-AND-ROUTE DESCRIPTION AND EXAMPLES*
PLACE-AND-ROUTE REFINEMENTS