I had surveyed the technical resources for applications of logic, and therefore applications of logic optimization using boundary techniques. It was clear that the hardest problems and the greatest need were in semiconductor design.

As we searched for funding sources, we articulated some specific applications. We had designed a high performance reconfigurable chip, but the big win was that the chip architecture was customized for boundary logic.

Optimization, layout and routing used unique iconic techniques. This approach solved some outstanding problems, such as ease of routing and stable timing.

Ease of routing: In today's reconfigurable chips, the area cost of routing is at least double that of the actual logic. As it turns out, the problem is not logic processing, it is getting signals from one gate to another. Boundary techniques confound logic functionality with interconnection, and ILOC could move fluidly between the two. We failed to make a convincing argument though, even by showing exact solutions -- industry wisdom is that routing is too difficult to fix. The lesson: don't try to change people's minds when speaking a foreign language.

Stable timing: ILOC logic configuration made it easy to assure a consistent chip timing, at least twice as fast as what was available from other automated techniques. The cost was that an engineer could not tweak the timing, to make a 300 MHz clock into a 310 MHz clock (even when existing tools provided only 80 MHz). Our solution was politically unacceptable. The lesson: don't try to make a job easier if it reduces perceived control.