Parens forms can be interpreted directly as logic gates, with nesting representing connecting wires. The parens boundary, then, is both logic and wiring, permitting a fluid design flow between area and connectivity optimization.

Containers can be interpreted as NOR gates (and dually as NAND gates), so that parens forms can be interpreted as homogeneous networks of simple gates.

The vast majority of my work in design optimization is not included on this site, for intellectual property protection. Here are a few pieces that have not yet been implemented.

Modeling Design Behavior

More to come...